1. Technical Field
The present invention relates to a semiconductor device manufacturing method, a semiconductor device, and a wiring board.
2. Related Art
Semiconductor packages are broadly categorized into peripheral type packages whose outside terminals are disposed in the periphery of a package and area type packages whose outside terminals are disposed below the undersurface of a package. Peripheral type packages are represented by a dual inline package (DIP), a small outline package (SOP), and a quad flat package (QFP) as shown in FIGS. 21A to 21C. For example, in FIG. 21D, a peripheral type package is manufactured by mounting an integrate circuit (IC) element 210 on a die pad 201 serving as a chip mounting part, then coupling an electrode of the IC element 210 and leads 203 of the a lead frame via gold wires or the like, and resin-sealing all these components except for portions of the outer peripheries of the leads 203. Portions of the leads 203 inside the resin package are called “inside terminals” and portions of the leads 203 outside the resin package are called “outside terminals.”
Area type packages are represented by ball grid array (BGA) packages as shown in FIGS. 22A, 22B, 23A, and 23B. For example, in these drawings, an area type package is manufactured by mounting the IC element 210 on the substrate 211, electrically coupling the substrate 211 and the IC element 210 via a gold wire, solder, or a gold bump, and resin-sealing the IC element 210 and the like. A BGA package in which the substrate 211 and the IC element 210 are coupled via a gold wire 213, as shown in FIGS. 22A and 22B, is also called a “gold wire BGA package.” A BGA package in which the substrate 211 and the IC element 210 are coupled via a bump 223, as shown in FIGS. 23A and 23B, is also called a “bump BGA package.” Among bump BGA packages is a type of bump BGA package that is not resin-sealed. The outside terminals of an area type package are not leads and, for example in FIGS. 23A to 23B, are electrodes (or solder balls) 225 mounted on the back of the substrate 211.
In recent years, a package is also manufactured, for example in FIG. 24A to 24I, by forming cylindrical terminals 233 and a die pad 235 on a metal plate 231 by electrical plating, then mounting the IC element 210 on the die pad 235, coupling the IC element 210 and the terminals 233 via the gold wires 213, then resin-sealing these components, removing the metal plate 231 from a resin molding 236, and cutting the resin molding 236 into individual products.
More specifically, in FIGS. 24A and 24B, first, a resist is applied onto the metal plate 231, and subjected to exposure and development so as to form a resist pattern 237. Next, as shown in FIG. 24C, for example, copper is formed on the surface of the metal plate 231 exposed from below the resist pattern 237 by electrical plating so as to form the cylindrical terminals 233 and the die pad 235. Then, as shown in FIG. 24D, the resist pattern is eliminated. Next, as shown in FIG. 24E, the IC element 210 is mounted on the die pad 235 formed by electrical plating, and wire-bonded to the terminals 233. Then, as shown in FIG. 24F, the IC element 210, the gold wires 213, and the like are resin-sealed. Next, as shown in FIG. 24G, the metal plate 231 is removed from the resin molding 236. Then, as shown in FIGS. 24H and 24I, margins are cut away from the resin molding 236 so as to complete the package.
Disclosed in JP-A-02-240940 is a technology that completes a peripheral type package by half-etching one surface of a supporter of a flat lead frame, then mounting an IC element on a die pad of the lead frame, subsequently wire-bonding and resin-sealing these components, and then grinding the other surface of the supporter to eliminate the supporter. Disclosed in JP-A-2004-281486 is a technology that attempts to enhance the general versatility of an area type package by disposing wiring from the center of a substrate outward in all directions in a plan view.
The related art examples, that is, peripheral type packages, area type packages, the package shown in FIGS. 24A to 24I, and the package described in JP-A-02-240940 all require a substrate serving as a mounting surface for an IC element, such as a die pad or an interposer, as well as requires a dedicated lead frame or substrate, or a dedicated photomask (to form a cylindrical terminal) according to the size of the IC element or the number of external outputs from the IC element (that is, the number of leads or balls). In particular, if small batches of a variety of products are manufactured, various lead frames or substrates, or various photomasks must be possessed. This prevents a reduction in manufacturing cost.
Also, in JP-A-02-240940, area type packages corresponding to various chip sizes are achieved by disposing wiring from the center of a substrate outward in all directions. However, this technology requires that the pad terminal of the IC element be disposed so as to always overlap the wiring extending from the center of the substrate outward in all directions in a plan view; therefore, flexibility in design is reduced with respect to the layout of the pad terminal. That is, the general versatility of the package is enhanced, while more limitations are imposed on the IC element.